The invention is related to the field of channel encoding digital bit streams for digital recording/reproducing.
Encoding/decoding n-bit source words into corresponding m-bit channel words, and vice versa, such that the conversion is parity inverting.
The invention relates to a device for encoding a stream of databits of a binary source signal into a stream of databits of a binary channel signal, wherein the bitstream of the source signal is divided into n-bit source words, which device comprises converting means adapted to convert said source words into corresponding m-bit channel words and to a method. The invention also relates to a device for decoding a stream of data bits of a binary channel signal obtained by means of the encoding device, so as to obtain a stream of databits of a binary source signal.
An encoding device mentioned in the foregoing is known from the book xe2x80x98Coding techniques for digital recordersxe2x80x99 by K. A. Schouhamer Immink, chapter 5.6.7, pp. 127 to 131, Prentice Hall (1991). The book discusses an encoder for generating a (d,k) sequence which satisfies the parameters: rate 2/3, (1,7), which encoder is also proposed by Cohn et al in U.S. Pat. No. 4,337,458. Those skilled in the art are hereby directed to European Patent Application 199.088 A2 and U.S. Pat. No. 5,477,222 to Kahlmann et. al.
The above citations are hereby incorporated in whole by reference.
The known encoding scheme suffers from the presence of a DC level which may become excessively large and therefore introduces distortion in communication systems which can not handle a DC component, as well as distortion in any recording of data in magnetic media.
The invention has for its object to provide a device for encoding n-bit source words into corresponding m-bit channel words, such that it itself does not generate a DC component in the channel signal, whereas further it provides the possibility, by means of additional measures to be taken, to realize a channel signal in the form of a (d,k) sequence.
The device in accordance with the invention is characterized in that the converting means are adapted to convert a block of p consecutive n-bit source words into a corresponding block of p consecutive m-bit channel words, such that the conversion for each block of p consecutive n-bit source words is parity inverting, where h, m and p are integers, m greater than nxe2x89xa71, pxe2x89xa71, and where p is an odd integer and can vary. xe2x80x98Parity invertingxe2x80x99 means that the parity of the n-bit source words to be converted are the inverse of the parity (after modulo-2 addition) of the corresponding m-bit channel words in which they are converted. As a result, a unique relationship between the parity of the source words and the parity of the channel words can be obtained, enabling an efficient DC control for the binary channel signal, after aT precoding.
The encoding device in accordance with the invention can be used in combination with a bit-adder unit in which one bit is added to codewords of a certain length. The signal obtained can be applied to the encoding device of the present invention. The channel signal of the encoding device is applied to a 1T-precoder. The purpose of the bit-adder unit is to add a xe2x80x980xe2x80x99- or a xe2x80x981xe2x80x99-bit to blocks of data in the input signal of the converter, so as to obtain a precoder output signal which is DC free, or includes a tracking pilot signal having a certain frequency. The precoder output signal is recorded on a record carrier. The adding of a xe2x80x980xe2x80x99-bit in the input signal of the converter results in the polarity of the output signal of the 1T precoder remaining the same. The adding of a xe2x80x981xe2x80x99-bit results in a polarity inversion in the output signal of the 1T precoder. The converter therefore influences the output signal of the 1T precoder such that the running digital sum value of the output signal of the 1T precoder can be controlled so as to have a desired pattern as a finction of time.
Because of the fact that the encoding device in accordance with the invention realizes a parity-inverting encoding, it does not influence the polarity of the signal it encodes and can therefore be used in combination with the bit-adder unit without the need of any modification.
Preferably, m equals n+1, and n is equal to 2. For n being equal to 1 or 2, the device in accordance with the invention can be used, with additional measures to be taken, as will become apparent later, for generating channel signals in the form of a (d,k) sequence, where d=1. Higher values for n do not allow for the generation of a (1,k) sequence. Further, n=1, which means that 1-bit source words are converted into 2-bit channel words, results in an increase of 100% in bits in the channel signal generated by the device. Contrary to this a conversion of 2-bit source words into 3-bit channel words results in an increase of only 50%, and is therefore more advantageous.
Various conversions of 2-bit source words into 3-bit channel words are possible, that have the parity inverting character. One such conversions is the subject of claim 4. It should however be noted that various permutations of the channel codes in the table are possible, namely in total 4.
The device in accordance with the invention wherein the converting means are adapted to convert 2-bit source words into corresponding 3-bit channel words, so as to obtain a channel signal in the form of a (d,k) sequence, where d=1, the device further comprising means for detecting the position in the bitstream of the source signal where encoding of single 2-bit source words into corresponding single channel words would lead to a violation of the d-constraint at the channel word boundaries and for supplying a control signal in response to said detection, may be further characterized in that in the absence of the control signal, the converting means are adapted to convert single 2-bit source words into corresponding single 3-bit channel words, such that the conversion for each 2-bit source word is parity inverting. More specifically, the device is characterized in that, in the presence of said control signal, the converting means are further adapted to convert the block of said two subsequent 2-bit source words into a corresponding block of two subsequent 3-bit channel words, such that the conversion for said block of two subsequent 2-bit source words is parity preserving. The measure to convert one (say: the second one) of two subsequent source words into a 3-bit word not identical to the four channel words CW1 to CW4, offers the possibility to detect at the receiver side that a situation existed that encoding of single source words into corresponding single channel words would have led to a violation of the d=1 constraint. The encoder now encodes a block of two 2-bit source words into a block of 2 3-bit channel words, such that the encoding of the block is parity preserving, whilst the d=1 constraint is satisfied as well.
To embody the encoding of blocks of two 2-bit source words, the device in accordance with the invention may be characterized in that the converting means are adapted to convert the blocks of two consecutive 2-bit source words into the blocks of two consecutive 3-bit channel words in accordance with the coding given in the following table:
The device in accordance with the invention, for generating a (d,k) sequence, wherein k has a value larger than 5, the device being further provided with means for detecting the position in the bitstream of the source signal where encoding of single 2-bit source words into single 3-bit channel words would lead to a violation of the k-constraint and for supplying a second control signal in response to said detection, may be further characterized in that, in the presence of the second control signal, occurring during the conversion of three consecutive 2-bit source words, the converting means are adapted to convert a block of said three consecutive 2-bit source words into a block of corresponding three consecutive 3-bit channel words, such that the conversion for said block of three 2-bit source words is parity inverting, the converting means are further adapted to convert two of the three source words in the block into corresponding 3-bit channel words not identical to the four channel words CW1 to CW4, in order to preserve the k constraint.
This measure enables an encoding of a block of three 2-bit source words into a block of three 3-bit channel words so as to satisfy the k-constraint, and such that the encoding is still parity inverting.
The measure to convert two (say: the second and the third one) of three subsequent source words into a 3-bit word not identical to the four channel words CW1 to CW4, offers the possibility to detect at the receiver side that a situation existed that the encoding of single 2-bit source words into corresponding single 3-bit channel words would have led to a violation of the k constraint. Upon detection, the decoder is capable of decoding the block of three 3-bit channel words into the corresponding block of three 2-bit source words in the inverse way, as upon encoding.
To embody the encoding of blocks of three 2-bit source words, the device in accordance with the invention may be characterized in that the converting means are adapted to convert blocks of three consecutive 2-bit source words into blocks of three consecutive 3-bit channel words in accordance with the coding given in the following table:
A device for decoding a stream of data bits of a binary channel signal into a stream of databits of a binary source signal, wherein the bitstream of the channel signal is divided into m-bit channel words, which device comprises deconverting means adapted to deconvert m-bit channel words into corresponding n-bit source words, is characterized in that, the deconverting means are adapted to deconvert a block of p consecutive m-bit channel words into a corresponding block of p consecutive n-bit source words, such that the conversion for each block of p consecutive m-bit channel words is parity inverting, where n, m and p are integers, m greater than n, pxe2x89xa71, and where p is an odd integer and can vary.
It should be noted that published European patent application 199.088A2 discloses a converter for converting n-bit source words into a channel signal in the form of a sequence of m-bit channel words, which channel signal is DC free. The conversion is however not parity inverting.